Recently, 3-D or 2.5-D stacked-type semiconductor devices (multichips) using TSVs (Through-Silicon Vias) are attracting attention from a viewpoint of high functionality and the like of semiconductor devices.
However, in a manufacturing process of the stacked-type semiconductor devices using TSVs, silicon substrates (chips) that hardly undergo elastic deformation have been electrically connected to one another with bumps. Since the silicon substrate hardly undergoes elastic deformation, the heights of the bumps have not been matched to one another in the plane of the silicon substrate when warpage of the silicon substrate is large. Further, the heights of the bumps not being matched to one another problematically causes difficulty in securing reliability of electric connection of the silicon substrates with bumps.
Due to this, in the stacked-type semiconductor devices, warpage of the semiconductor substrates is desired to be suppressed in order to secure reliability of electric connection of the semiconductor substrates.